1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly to a comparator circuit and a signal comparison method.
2. Description of the Related Art
In general, a comparator refers to a circuit, which compares analog signals inputted through two or more input terminals and transmits one of two values to an output terminal determined based on the comparison result. Here, the analog signal means a signal having a continuous magnitude during a given time. Furthermore, the output signal of the comparator is a digital signal having any one of the two values. The comparator may function as a kind of 1-bit analog to digital converter.
The comparator may be configured as an operational amplifier and the like. In a semiconductor circuit such as the operational amplifier, an offset voltage may occur due to an error in design or a package, a variation in semiconductor fabrication process or an external environment. Since an ideal comparator has no offset voltage, one of two values determined based on the magnitudes of inputted analog signals is outputted.
However, due to an offset voltage occurring in an operational amplifier or other circuits in the comparator, it may be difficult to accurately compare the magnitudes of the inputted analog signals.
FIG. 1 is a circuit diagram illustrating a conventional comparator circuit for compensating an offset voltage occurring in the comparator circuit.
Referring to FIG. 1, the comparator circuit includes an operational amplifier AMP, a capacitor COFF and first to third switches SW1 to SW3. The capacitor COFF is configured to store an offset voltage.
The comparator circuit of FIG. 1 performs an operation of comparing signals inputted to two input terminals I1 and I2, and the operation may be divided into first and second periods. The comparator circuit performs an offset storing operation of storing an offset voltage in the capacitor COFF during the first period, and performs a comparison operation of outputting a result obtained by comparing the signals inputted to the two input terminals I1 and I2 with reflection of the offset voltage stored in the capacitor COFF during the second period.
First, the offset store operation will be described. During the first period, the first and third switches SW1 and SW3 are turned on, and the second switch SW2 is turned off. For convenience of description, an offset voltage VOFF existing in the comparator circuit is represented by a DC voltage source OFFSET. During the first period, a voltage outputted to an output terminal OUT of the operational amplifier AMP is equal to the offset voltage VOFF. This is because the comparator circuit operates as a single gain loop. Therefore, the offset voltage VOFF outputted to the output terminal OUT of the operational amplifier is stored in the capacitor COFF by the operation of the first period.
Next, the comparison operation will be described. During the second period, the first and third switches SW1 and SW3 are turned off and the second switch SW2 is turned on. At this time, the offset voltage VOFF existing in the comparator circuit and represented by the DC voltage source OFFSET is connected to the first input terminal I2, and the capacitor COFF storing the offset voltage VOFF is connected to the second input terminal I1. Therefore, before input signals Vm and Vp are supplied to the first and second input terminals I1 and I2, the first and second input terminals I1 and I2 have the same potential. Therefore, the value outputted to the output terminal OUT of the operational amplifier during the comparison operation depends only on the result obtained by comparing the signals inputted to the first and second input terminals I1 and I2. That is, the offset voltage VOFF existing in the comparator circuit is compensated.
However, to compensate the offset voltage VOFF, the comparator circuit of FIG. 1 has to first perform the offset storing operation of storing the offset voltage VOFF in the capacitor COFF and then perform the comparison operation of comparing the input signals Vm and Vp. Therefore, the operation time for comparing the input signals may increase as a whole. Further, when a plurality of comparison operations are performed, temporal discontinuity occurs between time points at which the respective comparison results are generated.